Control and Data Dependence in Multithreaded Processors

Boosting instruction level parallelism in dynamically scheduled processors requires a large instruction window. The approach taken by current superscalar processors to build the instruction window is known to have important limitations, such as the requirement of more powerful instruction fetch mechanisms and the increasing complexity and delay of the issue logic. In this paper we present a novel processor architecture (which is called DeSM) based on a multithreaded execution model that takes a completely different approach to build a large instruction window. The idea is to identify at run-time sections of code that correspond to loops and execute concurrently several iterations even if they are dependent. Unlike superscalar processors, instructions are not decoded in sequential order and thus, the dependence checking mechanism of superscalar processors would not work for DeSM processors. In a DeSM processor, interthread dependences are speculated (i.e. they are predicted and instructions are executing obeying the predicted dependences). Besides, a DeSM processor significantly reduces the required instruction fetch bandwidth since it takes advantage from the fact that the multiple threads of control share a common code (they are executing different iterations of the same loop). The novel features of the DeSM rely on hardware mechanisms that do not require any special feature in the instruction set architecture nor compiler support.